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AL4CS211 al4cs221 al4cs231 al4cs241 al4cs251 data sheets version 1.1
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 2 amendments 07.11.01 preliminary version 1.0 10.17.01 version 1.1, added dc and ac timing data
AL4CS211/al4cs221/al4cs2 31/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 3 AL4CS211/al4cs221/al4cs231/al4cs241/ al4cs251 (512 x9, 1k x9, 2k x9, 4k x9, 8k x9) synchronous fifo contents: 1.0 description ________________________________ ________________________________ 4 2.0 features ________________________________ ________________________________ ___ 4 3.0 applications ________________________________ ________________________________ 4 4.0 chip information ________________________________ ___________________________ 5 4.1 marking information ________________________________ _____________________________ 5 4.1 ordering information ________________________________ _____________________________ 5 5.0 pin - out diagram ________________________________ ____________________________ 6 6.0 block diagram ________________________________ _____________________________ 6 7.0 pin definition and descr iption ________________________________ ________________ 7 8.0 memory operations ________________________________ _________________________ 8 8.1 inputs and outputs ________________________________ _______________________________ 8 8.2 con trols ________________________________ ________________________________ ________ 9 8.3 flags ________________________________ ________________________________ __________ 11 9.0 multiple devices bus expansion a nd cascading ________________________________ _ 12 9.1 width expansion configuration ________________________________ ___________________ 12 9.2 depth expansion ________________________________ ________________________________ 12 10.0 electrical characte ristics ________________________________ ___________________ 14 10.1 absolute maximum ratings ________________________________ ______________________ 14 10.2 recommended operating conditions ________________________________ ______________ 14 10.3 dc characteristics ________________________________ _____________________________ 14 10.4 ac electrical characteristics ________________________________ _____________________ 15 10.5 timing diagrams ________________________________ _______________________________ 16 11.0 mecha nical drawing ________________________________ ______________________ 23 11.1 7x7mm 32 - pin tqfp package ________________________________ ____________________ 23 11.2 32 - pin plcc package ________________________________ ___________________________ 24
AL4CS211/al4cs221/al4cs2 31/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 4 1.0 description the AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 series memory products are high - performance, low - power 9 - bit read/write fifo (first - in - first - out) memory chips. they are specially designed to buffer high speed streaming data for a wide range of communic ation applications, such as optical disk controllers, local area networks (lans), sonet (synchronous optical network). the input data is synchronous with a free - running clock (wclk), and input - enable pins (/wen1, /wen2). data is written into the fifo on every clock when enable pins are asserted. the output is synchronous with the other free - running clock (rclk) and enables (/ren1, /ren2). an output enable pin (/oe) is provided at the read port for tri - state control of the output port. the fifos can o utput two fixed flags, empty flag( /ef) and full flag (/ff), and two programmable flags, almost - empty (/pae) and almost - full (/paf). the offsets of the /pae and /paf flags are loaded when load pin (/ld) goes low. 2.0 features 512 x9 - bit cell array (a l4cs211) 1,024 x9 - bit cell array (al4cs221) 2,048 x9 - bit cell array (al4cs231) 4,096 x9 - bit cell array (al4cs241) 8,192 x9 - bit cell array (al4cs251) 100/133 mhz operation 10/7.5 ns read/write cycle time independent read and write operations empty and full flags support programmable almost - empty and almost - full flags output enable (data skipping) 3.3v power supply with 5v tolerant available in a 32 - pin thin quad flat pack (tqfp) and 32 - pin plastic leaded chip carrier (plcc) packages 3.0 applications rout ers atm switches cable modems wireless base stations sonet(synchronous optical network) multiplexers multimedia systems time base correction (tbc)
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 5 4.0 chip information 4.1 marking information al4cs2 x 1 x - xx - xx xxxx xxxxx part number: x = 1, 2, 3, 4, 5 as AL4CS211, al4cs221, al4cs231, al4cs241, al4cs251 package: xx = j: plcc pf: tqfp speed grade: xx = -10, -7.5, .. version number: x = a, b, c.. lot number date code 4.1 ordering information the ord ering information for AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 are: part number package power supply status AL4CS211/221/231/241/251(a - 10 - pf) 32 - pin plastic tqfp(7x7mm) +3.3v 10% sample in aug., 2001 AL4CS211/221/231/241/251(a - 7.5 - pf) 32 - pin plas tic tqfp(7x7mm) +3.3v 10% sample in aug., 2001 AL4CS211/221/231/241/251(a - 10 - j) 32 - pin plastic plcc +3.3v 10% sample in aug., 2001 AL4CS211/221/231/241/251(a - 7.5 - j) 32 - pin plastic plcc +3.3v 10% sample in aug., 2001
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 6 5.0 pin - out diagram the a l4cs211/al4cs221/al4cs231/al4cs241/al4cs251 pin - out diagram is following: tqfp package top view averlogic al4cs2x1 x-xx-xx xxxx xxxx 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 d1 d0 /paf /pae gnd /ren1 rclk /ren2 /ff q0 q1 q2 q3 /oe /ef q4 16 15 14 13 12 11 10 9 d2 d3 d7 /rs d8 d4 d5 d6 25 26 27 28 29 30 31 32 /wen1 wclk wen2 vcc q8 q7 q6 q5 13 30 4 1 21 20 14 averlogic al4cs2x1 x-xx-xx xxxx xxxx 31 32 2 3 15 16 17 18 19 22 23 24 25 26 27 28 29 12 11 10 9 8 7 6 5 q2 q1 q0 /ff /ef q3 q4 d6 d5 d4 d3 d8 d2 d7 /oe /ren2 rclk /ren1 gnd /pae /paf d0 d1 q5 q6 q7 q8 vcc wen2 wclk /wen1 /rs plcc package top view 6.0 block diagram (512, 1k ,2k, 4k, 8k) x9 memory array input buffer output buffer write control logic read control logic flag logic write pointer read pointer offset regissers reset logic input data bus output data bus /oe wclk /wen1 /ld /rs rclk /ren1 /ff /ef /paf /pae figure 1. al4cs2x1 fifo block diagram wen2 /ren2 the internal structure of the AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 consists of input/output buf fers, read/write control logic and main (512, 1k, 2k, 4k, 8k) x9 different configuration memory cell array and state - of - the - art logic design that takes care of addressing and controlling the read/write data.
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 7 7.0 pin definition and description the pin - out definition and function are described as following: write bus signals pin symbol pin name tqfp pin no. plcc pin no. i/o typ description d[8:0] data inputs [26:32], 1, 2 [30:32], [1:6] i 9 - bit input data bus. /wen1 write enable 24 28 i /wen1 is the on ly write enable pin, if fifo is configured to support programmable flags. when /wen1 is low, data is written into the fifo on every rising edge of wclk. if the fifo is configured to have two write enables, /wen1 must be low and wen2 must be high to write data into the fifo. when fifo is full (/ff = low), data will not be written into fifo. wen2 write enable 22 26 i the fifo is configured at the reset to either have two write enables or support programmable flags. if write enable 2 (wen2) is high at reset (/rs = low), this pin will operate as a second write enable pin. if write enable 2 (wen2) is low at reset (/rs = low), the fifo is configured to support programmable flags function and /wen1 is the only write enable pin. wc lk write clock 23 27 i data is written into the fifo on a rising edge of wclk when the write enable(s) are asserted. data will not be written into fifo if /ff is not low. read bus signals pin symbol pin name tqfp pin no. plcc pin no. i/o typ descripti on q[8:0] data outputs [21:12] [24:16] o 9 - bit output data bus. /ren1 read enable 6 10 i when both /ren1 and /ren2 are low, data is read from the fifo on every rising edge of rclk. data will not be read from the fifo if the /ef is low.
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 8 /ren2 read enable 8 12 i when /ren1 and /ren2 are low, data is read from the fifo on every rising edge of rclk. data will not be read from the fifo if the /ef is low. /oe output enable 9 13 i when /oe is low, the data output bus is active. if /oe is high, the output data bus will be in high - impedance. rclk read clock 7 11 i data is read from the fifo on a rising edge of rclk when /ren1 and /ren2 are low, and if the fifo is not empty. miscellaneous & flags signals pin symbol pin name tqfp pin no. plcc pin no. i/o typ description /rs reset 25 29 i when /rs is set low, internal read and write pointers are set to the first location of the ram array, /ff and /paf go high, and /pae and /ef go low. a reset is required before an initial write after power - up. /ff full flag 11 15 o /ff indicates whether or not the fifo memory is full. /ef empty flag 10 14 o /ef indicates whether or not the fifo memory is empty. /pae programmabl e almost - full flag 4 8 o when /pae is low, the fifo is almost - empty based on the offset program med into the fifo. /paf programmabl e almost - full flag 3 7 o when /paf is low, the fifo is almost ? full based on the offset programmed into the fifo. power/ground signals pin symbol pin name tqfp pin no. plcc pin no. i/o typ description vcc power 21 25 - 3.3v 10% power supply gnd ground 5 9 - ground. 8.0 memory operations 8.1 inputs and outputs 8.1.1 data inputs (d8 ~ d0) d8 ~ d0 are 9 - bit wide of input data port.
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 9 8.1.2 data outputs (q8 - q0) q 8 ~ q0 are 9 - bit wide of output data port. 8.2 con trols 8.2.1 reset (/rs) reset takes place when the reset (/rs) input is low. during reset, both internal read and write pointers are set to the staring position. a reset is required to initial internal logic after power - up. the full flag (/ff) and progr ammable almost - full flag (/paf) will be reset to high after t rsf . the empty flag (/ef) and programmable almost - empty flag (/pae) will be reset to low after t rsf . during reset, the output register is initialized to all zeros and the offset registers are in itialized to their default values. 8.2.2 write clock (wclk) a write cycle is initiated on the rising edge of the write clock (wclk). data setup and hold times must be met with respect to the rising edge of wclk. the full flag (/ff) and programmable almos t - full flag (/paf) are synchronized with respect to the rising edge of the write clock (wclk). the write and read clocks can be asynchronous or coincident. 8.2.3 write enable1 (/wen1) if the fifo is configured to support programmable flags, write enable 1 (/wen1) is the only enable control pin. in this configuration, when write enable 1 (/wen1) is low, data can be written into the input register and memory array on the rising edge of every write clock (wclk). data is stored in the memory array sequentiall y and independently of any on going read operation. when write enable 1 (/wen1) is high, the input holds the previous data and no new data can be written into the memory array. if the fifo is configured to have two write enables, which allows for depth e xpansion, two enable control pins are involved in the write operations. please refer write enable 2 (wen2) section for details. to prevent data overflow, the full flag (/ff) will go low, inhibiting further write operations. upon the completion of a vali d read cycle, the full flag (/ff) will go high after t wff , allowing a valid write to begin. write enable(s) are ignored when the fifo is full. 8.2.4 read clock (rclk) data can be read on the outputs on the rising edge of the read clock (rclk), when all t he output controls /ren1, /ren2, output enable (/oe) are set low. the empty flag (/ef) and programmable almost - empty flag (/pae) are synchronized with respect to the rising edge of the read clock (rclk). the write and read clocks can be asynchronous or c oincident. 8.2.5 read enable (/ren1, /ren2) when both read enables (/ren1, /ren2) are low, data is read from the memory array to the output register on the rising edge of the read clock (rclk). when either read enable (/ren1, /ren2) is high, the output r egister holds the previous data and no new data can to be loaded into the register. when all the data has been read from the fifo, the empty flag (/ef) will go low, inhibiting further read operations. once a valid write operation has been done, the empty flag (/ef) will go high after t ref and a valid read can begin. the read enables (/ren1, /ren2) are ignored when the fifo is empty.
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 10 8.2.6 output enable (/oe) when output enable (/oe) is enabled (low), the parallel output buffers receive data from the out put register. when /oe is disabled (high), the q8 ~ q0 output data bus is in a high - impedance state. 8.2.7 write enable2 & /ld (wen2) this is a dual - purpose pin. the fifo can be configured at reset to have programmable flags or to have two write enab les, which allows depth expansion. 2 write enable configuration if write enable 2 (wen2) is set high at reset (/rs = low), this pin operates as a second write enable pin. in this configuration, when write enable (/wen1) is low and write enab le 2 (wen2) is high, data can be written into the fifo on the rising edge of every write clock (wclk). data is stored in fifo sequentially and independently of any on - going read operation. when write enable (/wen1) is high and/or write enable 2 (wen2) is low, the input register holds the previous data and no new data is allowed to be written into the fifo. to prevent data overflow, the full flag (/ff) will go low, inhibiting further write operations. upon the completion of a valid r ead cycle, the full flag (/ff) will go high after t wff , allowing a valid write to begin. write enable 1 (/wen1) and write enable 2 (wen2) are ignored when the fifo is full. single write enable and programmable flags support configuration the fifo is configured to have programmable flags when the write enable2 (wen2) is set to low at reset (/rs = low). the AL4CS211/221/231/241/251 devices contain four 8 - bit offset registers, which can be loaded with data on the inputs, or read from the outputs. see following table for details of the size of the registers and the default values. 1 st word 2 nd word 3 rd word 4 th word [7:0] empty offset (lsb) [0] empty offset (msb) [7:0] full offset (lsb) [0] full offset (msb) AL4CS211 default = 07h default = 0b default = 07h default = 0b [7:0] empty offset (lsb) [1:0] empty offset (msb) [7:0] full offset (lsb) [1:0] full offset (msb) al4cs221 default = 07h default = 00b default = 07h default = 00b [7:0] empty offset (lsb) [2:0] empty offset (msb) [7:0] full offset (lsb) [2:0] full offset (msb) al4cs231 default = 07h default = 000b default = 07h default = 000b [7:0] empty offset (lsb) [3:0] empty offset (msb) [7:0] full offset (lsb) [3:0] full offset (msb) al4cs241 default = 07h default = 0000b default = 07h default = 0000b [7:0] empty offset (lsb) [4:0] empty offset (msb) [7:0] full offset (lsb) [4:0] full offset (msb) al4cs251 default = 07h default = 00000b default = 07h default = 00000b in this configured, when the write enable1 (/ wen1) and write enable 2 (wen2) are set low, data on the inputs d8 ~ d0 is written into the empty (least significant bit) offset register on the first rising edge of the write clock (wclk). data is written into the empty (most significant bit) offset register on the second rising edge of the write clock (wclk), into the full (least significant bit) offset register on the third transition, and into the full (most significant bit) offset register on the fourth transition. the fifth transition of the write clock (wclk) again writes to the empty (least significant bit) offset register.
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 11 however, writing all offset registers does not have to occur consecutively. the fifo can return to normal read/write operation by bringing the write enable 2 (wen2) pin high after one or two offset registers can be written. when the write enable 2/load (wen2/ld) pin is set low again, and write enable 1 (/wen1) is low, the next offset register in sequence is written. the contents of the offset registers c an be read on the output lines when the write enable 2 (wen2) pin is set low and both read enables (/ren1, /ren2) are low. data can be read on the rising edge of the read clock (rclk). a read and write to the offset registers should not be per formed simultaneously. 8.3 flags 8.3.1 full flag (/ff) the full flag (/ff) will go low, inhibiting further write operation, when the device is full. if no reads are performed after reset (/rs), the full flag (/ff) will go low after 512 writes for the al 4cs211, 1,024 writes for the al4cs221, 2,048 writes for the al4cs231, 4,096 writes for the al4cs241 and 8,192 writes for the al4cs251. the full flag (/ff) is synchronized with respect to the rising edge of the write clock (wclk). 8.3.2 empty flag (/ef) t he empty flag (/ef) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. the empty flag (/ef) is synchronized with respect to the rising edge of the read clock (rclk). 8.3.3 programmable almost - full flag (/paf) the programmable almost - full flag (/paf) will go low when the fifo reaches the almost - full condition. if no reads are performed after reset (/rs), the programmable almost - full flag (/paf) will go low after (512 - m) wr ites for the AL4CS211, (1,024 - m) writes for the al4cs221, (2,048 - m) writes for the al4cs231, (4,096 - m) writes for the al4cs241 and (8,192 - m) writes for the al4cs251. the offset ?m? is defined in the full offset registers. if there is no full offset speci fied, the programmable almost - full flag (/paf) will go low at full - 7 words. the programmable almost - full flag (/paf) is synchronized with respect to the rising edge of the write clock (wclk). 8.3.4 programmable almost - empty flag (/pae) the programmable a lmost - empty flag (/pae) will go low when the read pointer is "n+1" locations less than the write pointer. the offset "n" is defined in the empty offset registers. if no reads are performed after reset the programmable almost - empty flag (/pae) will go hig h after "n+1" for the AL4CS211/221/231/241/251. if there is no empty offset specified, the programmable almost - empty flag (/pae) will go low at empty+7 words. the programmable almost - empty flag (/pae) is synchronized with respect to the rising edge of th e read clock (rclk).
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 12 9.0 multiple devices bus expansion and cascading 9.1 width expansion configuration simply connecting the corresponding input controls signals of multiple devices may increase data bus width. a composite flag should be created for e ach of the end - point status flags (/ef and /ff). the partial status flags (/pae and /paf) can be detected from any one device. figure 15 demonstrates an 18 - bit word width data bus by using two AL4CS211/221/231/241/251s. any word width expansion can be a ttained by adding additional AL4CS211/221/231/241/251s. when these devices are in a width expansion configuration, the read enable 2 (/ren2) control input can be grounded (see figure 15). in this configuration, thewriteenable2 (wen2) pin is se t low at reset so that the pin operates as a control to load and read the programmable flag offsets. al4cs2x1 /wen1 wclk q[8:0] wen2 /pae rclk /ren1 /oe /rs /ff /paf /ef d[8:0] /ren2 al4cs2x1 /wen1 wclk q[8:0] wen2 /pae rclk /ren1 /oe /rs /ff /paf /ef d[8:0] /ren2 write clock write enable write enable2 programmable write controls write controls gnd read controls read clock read enable output enable programmable read controls empty flag/ output ready 18-bit data in bus 18-bit data out bus full flag/ input ready reset reset 9-bit 9-bit figure 2. multiple fifo memory with programmable flags used in depth expansion configuration gnd 9.2 depth expansion the depth expansion of AL4CS211/221/231/241/251 is also possible. the existence of two enable pins on the read and write port allow depth expansion. the write enable 2 pin is used as a second write enable in a depth expansion configuration thus the programmable flags are set to the default values. depth expansion is possible by using one enable in put for system control while the other enable input is controlled by expansion logic to direct the flow of data. a typical application would have the expansion logic alternate data access from one device to the next in a sequential manner. these fifos op erate in the depth expansion configuration when the following conditions are met:
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 13 1. the wen2 pin is held high during reset so that this pin operates a second write enable. 2. external logic is used to control the flow of data.
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 14 10.0 electrical characte ristics 10.1 absolute maximum ratings parameter 3.3v rating unit v dd supply voltage - 0.3 ~ +3.8 v v p pin voltage - 0.3 ~ +(v dd +0.3) v i o output current - 20 ~ +20 ma t amb ambient op. temperature 0 ~ +85 c t stg storage temperature - 40 ~ +125 c 10.2 recommended operating conditions 3.3v rating parameter min typ max unit v dd supply voltage +3.0 +3.3 +3.6 v v ih high level input voltage 0.7 v dd v dd v v il low level input voltage 0 0.3 v dd v 10.3 dc characteristics ( v dd = 3.3v, vss=0v. t amb = 0 to 70c) 3.3v rating parameter min typ max unit i dd operating current @20mhz - - 16 ma i dds standby current - 1.8 5 ma v oh hi - level output voltage 2.4 - v dd v v ol lo - level output voltage - - +0.4 v i li input leakage current - 2 - +2 m a i lo output leakage current - 10 - +10 m a note: the operating current is tested at rclk=wclk=20mhz and data inputs switch at 10mhz
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 15 10.4 ac electrical characteristics ( v dd = 3.3v, vss=0v, t amb = 0 to 70c) 100mhz 133mhz symbol parameter min max min max unit t s c lock cycle frequency - 100 - 133 mhz t a data access time 2 7.5 2 5 ns t clk clock cycle time 10 - 7.5 - ns t clkh clock high time 4.5 - 3.5 - ns t clkl clock low time 4.5 - 3.5 - ns t ds data setup time 3 - 2.5 - ns t dh data hold time 0.5 - 0.5 - ns t en s enable setup time 3 - 2.5 - ns t enh enable hold time 0.5 - 0.5 - ns t rs reset pulse width 10 - 7.5 - ns t rss reset setup time 8 - 6 - ns t rsr reset recovery time 8 - 6 - ns t rsf reset to flag and output time - 10 - 9 ns t olz output enable to output in low - z 0 - 0 - ns t oe output enable to output valid - 6 - 5 ns t ohz output enable to in high - z - 6 - 5 ns t wff write clock to full flag - 7 - 5 ns t ref read clock to empty flag - 7 - 5 ns t af write clock to almost - full flag - 7 - 5 ns t ae read cl ock to almost - empty flag - 7 - 5 ns t skew1 skew time between read clock & write clock for /ff & /ef 5 - 3 - ns t skew2 skew time between read clock & write clock for /pae and /paf 10 - 8 - ns
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 16 10.5 timing diagrams /ff,/paf /ef,/ pae q0~a8 figure 3. reset timing /rs /ren1, /ren2 /wen1 wen2 t rsf t rsf t rsf /oe = 1 /oe = 0 t rs t rsr t rss t rsr t rsr t rss t rss
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 17 rclk /ren1, /ren2 /ef q0 ~ q8 /oe wclk t clk t clkl t clkh figure 4. read cycle timing /wen1 valid data t skew1 t oe t olz t ohz t a t ref t enh t ens t ref no operation wen2
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 18 q0 ~ q8 /oe figure 5. first data word latency timing wclk d0 ~ d8 /wen1 rclk /ef /ren1, /ren2 t frl t skew1 d0 d1 d2 d3 d4 d0 d1 t ds t ens t re f t ens t a t a t oe t olz t ens wen2
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 19 oe q0 ~ q8 figure 6. full flag timing wclk d0 ~ d8 /ff wen2 rclk /ren1, /ren2 data read next data t skew 1 data in output buffer data write data write t wff t ds t wff t skew1 t wff t ds t ens t enh t a t ens t enh t a /wen1 t enh t enh t ens t ens
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 20 oe q0 ~ q8 figure 7. empty flag timing wclk d0 ~ d8 /wen1 rclk /ef /ren1, /ren2 t ens data in output buffer data write t enh t ds t ens t enh t skew1 t ds t a t ref t ref data write data read t frl t ref t skew1 t frl wen2 t ens t enh t ens t enh /wen1 d0 ~ d7 figure 8. write offset registers wclk /ld pae offset (lsb) t ds pae offset (msb) paf offset (lsb) t ens t en h t dh paf offset (msb)
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 21 /ren1, /ren2 q0 ~ q7 figure 9. read offset registers timing rclk /ld data output paf offset t ens t en h t a empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb) /pae rclk figure 10. programmable empty flag timing wclk /wen1 t ens t en h /ren1, /ren2 n words in fifo n+1 words in fifo t ens t en h t paes t skew2 t paes wen2 t ens t en h
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 22 /paf rclk figure 11. programmable full flag timing wclk /wen1 t ens t en h /ren1, /ren2 t ens t en h full - (m + 1) words in fifo full - m words in fifo t pafs t pafs t skew2 t ens t en h wen2
AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 AL4CS211/al4cs221/al4cs231/al4cs241/al4cs251 december 14, 2001 23 11.0 mecha nical drawing 11.1 7x7mm 32 - pin tqfp package
11.2 32 - pin plcc package
contact information averlogic technologies, inc. 90 great oaks blvd. #204 san jose, ca 95119 usa tel : +1 408 361 - 0400 fax : +1 408 361 - 0404 e - mail : sales@averlogic.com url : www.averlogic.com averlogic technologies, corp. 4f., no.514, sec.2, cheng kung rd., nei - hu dist., taipei, taiwan r.o.c tel : +886 2 - 27915050 fax : +886 2 - 27912132 e - mail : sales@averlogic.com.tw url : www.averlogic.com.tw

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